This application is related to Japanese Patent Application No. 2000-194455 filed on Jun. 28, 2000, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a process for fabricating a MOS semiconductor transistor, more particularly, a process for fabricating a MOS semiconductor transistor having an LDD structure.
2. Description of Related Art
A conventional process for fabricating a MOS semiconductor transistor having the LDD structure is explained with reference to FIGS. 2(a) to 2(d) (see Japanese Unexamined Patent Publication No. HEI 3(1991)-87060).
FIGS. 2(a) to 2(d) are schematic sectional views illustrating the conventional process for fabricating a device.
First, as shown in FIG. 2(a), a device isolation region 3 and a gate insulating film 4 are formed on a semiconductor substrate 1 of a first conductivity type. Next, a gate electrode 5 is formed of polycrystalline silicon, and the upper face and side faces of the gate electrode 5 are thermally oxidized to form a thermally oxidized film 6. Thereafter, a nitride film 7 is formed to a thickness of about 200 nm by a CVD method.
Next, as shown in FIG. 2(b), the nitride film 7 is anisotropically etched selectively to form a sidewall spacer 7a of the nitride film. Then, exposed surfaces of the gate electrode 5 and the semiconductor substrate 1 are thermally oxidized thinly to form a thermally oxidized film 6a. Thereafter, only a desired region is opened using a photoresist mask 8, and an impurity of a second conductivity type which is reverse to the conductivity type of the semiconductor substrate is implanted into the semiconductor substrate to form a high-concentration impurity layer 9.
Next, as shown in FIG. 2(c), the sidewall spacer 7a is isotropically etched out under the condition that the etching rate of the nitride film is sufficiently larger than the etching rate of the oxide film. Subsequently, an impurity of a second conductivity type is implanted in a low concentration to form a low-concentration impurity layer 10.
Next, as shown in FIG. 2(d), the photoresist mask 8 is removed, and the resulting semiconductor substrate is annealed, to complete the MOS semiconductor transistor of the LDD structure.
In the above-explained conventional process for fabricating a MOS semiconductor transistor having the LDD structure, the sidewall spacer is formed of a thick nitride film since the sidewall spacer needs to be selectively removed. However, the thick nitride film has a significantly large stress, and its formation damages the semiconductor substrate and deteriorates the characteristics of the transistor.
In addition, after the etching of the sidewall spacer, the thermally oxidized film 6a needs to be formed for protection of the surface of the gate electrode and the surface of the resulting semiconductor. This thermally oxidized film 6a is also formed thinly on the surface of the sidewall spacer formed of the nitride film. Accordingly, the thin oxide film needs to be removed prior to etching the nitride film at a high selective ratio. Further, the etching rate becomes low when the nitride film is dry-etched at a high selective ratio with respect to the oxide film. Therefore, productivity declines.
Accordingly, the present invention provides a process for fabricating a MOS semiconductor transistor which includes a first oxide film on a semiconductor substrate and on a surface of a gate electrode formed on the semiconductor substrate with intervention of a gate insulating film, a nitride film on the first oxide film and a sidewall spacer of a second oxide film formed on a side of the gate electrode with intervention of the first oxide film and the nitride film, the process comprising the steps of:
forming, on the nitride film, a photoresist mask which has an opening in a device formation region;
implanting impurity ions through the nitride film and the first oxide film into the semiconductor substrate in a high concentration using the gate electrode, the sidewall spacer and the photoresist mask as a mask;
selectively removing the sidewall spacer from the device formation region by wet etching;
implanting impurity ions into the semiconductor substrate in a low concentration using the gate electrode and the photoresist mask as a mask, thereby forming an LDD structure;
removing the photoresist mask; and
thermally treating the resulting semiconductor substrate.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.